Analog Design with Synopsys Custom Designer

Maximum limit of participants: 30

Objectives

  • Provide a short overview of analog design basics.
  • Introduce the tools that aid analog designers through a full IC implementation.
  • Deliver lab experiences so users can familiarize with Analog IC Design flow.

Topics

  • Introduction to semiconductors devices and analog design flow.
  • Overview of Synopsys Tools (Design Compiler, Custom Explorer, HSpice, IC Validator, Star RCXT)
  • Using Design Compiler (Schematic Editor, Layout Editor, SAE, etc).
  • Ideal Amplifiers and Amplifiers using Transistors.
  • Generation and Analysis of Curves.
  • Entire Design Flow.
  • vOptional labs and project.

      Synopsys Tools Training Program

      The first day of the workshop is focused on a quick review related to semiconductor devices, the introduction to the analog design and a fast overview of the IC fabrication. The first laboratory experience is based on the usage of “Custom Designer”, specifically the “Schematic Editor” and “SAE” (“Simulation and Analysis Environment”). Simulations like “tran”, “ac” and “dc” are created in this experience.

      The second day is focused on explain the entire analog design process and shows some “Custom Designer” features. The laboratory experience this day is based on the usage of “Layout Editor” to create an amplifier using transistors. This laboratory also includes the first verification step, the “DRC” (“Design Rules Check”) verification, using the “IC Validator” tool. The “op” simulation using “SAE” is used at the final of this experience.

      The third day is focused only in laboratory experiences. The lab 3 is related to generate curves that characterize a device and aid the design process. The lab 4 is the final one and uses the “DRC” verification again and adds a new step, the “LVS” (“Layout Versus Schematic”) verification. This new step is also implemented using the “IC Validator” tool. After these verifications, the extraction of parasitic RCs for the interconnections is performed using the “Star RCXT” tool. Finally this data is used to perform post-layout simulations.

      Lecturers

      -Ing. Victor Grimblatt, Synopsys Inc., Chile.
      -Ing. Ronald Valenzuela, Synopsys Inc., Chile.
      -Ing. Esteban Viveros, Synopsys Inc., Chile.

      Class materials

      All the material will be provided to students during the EAMTA.

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