Maximum limit of participants: 30


To prepare the student to be an entry-level industrial standard cell ASIC designer.
To give the student an understanding of issues and tools related to ASIC design and implementation including timing, performance and power optimization, verification and manufacturing test.
To give students the understanding, theory, and tools necessary to design large-scale digital system VLSI design for architectures that have millions or billions of transistors
To use a Hardware Design Language (Verilog) for digital design
To understand different design metrics: component/gate count and implementation area, switching speed, energy dissipation and power


Introduction to digital world and ASIC design flow
Design of digital hardware using Verilog HDL
Finite State Machines
Timing Design
Hierarchy and Partitioning
Low Power Design
Test Benches and Verification


The track considers labs where the students will develop specific modules using Verilog and state-of-art design tools


Victor Grimblatt
Victor has a Microelectronic Engineering degree from the Institut National Polytechnique de Grenoble (France) and an Electronics Engineer degree from Universidad Santa Maria (Valparaiso, Chile). He has more than 20 years experience in the electronics and information technology industry working in several international companies such as VLSI technology Inc, Compass design Automation Inc, Honeywell Bull, Motorola and Synopsys Inc. in France, USA, and Chile. He is now managing an R&D Center Synopsys opens in Chile. He is also professor at Universidad de Chile and Universidad de los Andes where he lecture courses related to Digital Systems, Computer Architecture, Integrated Circuit Design, and Embedded Systems.

To be defined
To be defined

Class materials

All the material will be provided to students during the EAMTA.


M.D. Ciletti, “Advanced Digital Design with the Verilog HDL,” (Prentice Hall), 2003. ISBN 0-13-089161-4.
D.R. Smith and P.D. Franzon, “Verilog Styles for Synthesis,” (Pearson Education [Prentice Hall]), 2000.ISBN. 0-201-61860-5.
Thomas and Moorby, “The Verilog Hardware Description Language”, 3rd edition, Kluwer Academic. ISBN 0-7923-9723-1.
S. Sutherland, S. Davidman, P. Flake, “System Verilog for Design” (Kluwer), 2004, ISBN 1-4020-7350-8.
H. Bhatnagar, “Advanced ASIC Chip Synthesis Using Synopsys Design Compiler, Physical Compiler, and PrimeTime”, ISBN 0-7923-7644-7.
Samir Palnitkar, “Verilog HDL” (Prentice Hall), 2008. ISBN 0-13-044911-3
John Willimas, “Digital VLSI Desing with Verilog” (Springer), 2008, ISBN 978-1-4020-8445-4

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