Basic Digital Design

Goal and abstract

The course aims to teach the basics of digital design, not to learn an HDL language.

In the first part the basic elements for the digital design are presented: Combinational circuits and sequential circuits.

A second instance is use to explain how to design a synchronous circuit correctly. This is to take into account the timing and delays of gates and signals, in order to make a circuit work logically well and efficiently from a time (or speed) point of view.

In a third instance, the design of some simple synchronous circuit will be implemented and simulated to verify its operation.

Minimum Content

First part:

Binary representation, fixed point and floating point.
Arithmetic in representation systems.
Elements of digital design:
- Combinational circuits: gates, generics (logic functions), multiplexors, comparators, adders.
- Sequential circuits: latch, flip-flip, register, memories.
- Complexes: Multipliers, FIFO, State Machines (FSM).

Temporal diagrams of combinational and sequential circuits.
Examples combining basic elements to form other complex elements: FF with enable, flank detectors, counters, multipliers, CORDIC, FIR and IIR filter and others.

Second part:

Timing of the circuits.
Synchronous circuits.
- Asynchronous signals of a digital synchronous circuit: clk and arst.

Delay of the gates:
- Load and current management of a damper.
- Delay models of a damper.

Characteristic times of the FF.

Third part:

Hardware Description Language: VHDL and verilog.

Using the two languages ​​show examples of HW description types:
- Definition of ports.
- Functional description: Concurrent vs. “Sequential” (process / always).

Examples with the two languages:
- How to synthesize combinational logic:
- Concurrent.
- “Sequential”.
- Synthesize memory elements

Schedule

Download the schedule in this link!

Teaching Team

Dr. Ing. Ariel L. Pola (Clariphy-Fundación Fulgor) was born in Rio Cuarto, Argentina, in 1983. He received the Telecommunication Engineer degree from the Universidad Nacional de Rio Cuarto, Argentina, in 2008 and his Ph.D degree in engineering from the Universidad Nacional del Sur, Bahia Blanca, Argentina from 2016.

In 2009 he obtained a doctoral scholarship from the National Agency for the development of his thesis on “Reduced Complexity Architectures for Electronic Compensation Dispersion in High Speed Communications Systems” and in 2016 obtained the title of PhD in Engineering from the Universidad Nacional del Sur.

Since 2012, it has actively participated in the organization of the Argentine School of Micro-Nanocelectronics, Technology and Applications (EAMTA) and its associated CAMTA conference, whose objective is to promote the area between undergraduate and graduate students of the country and the region.

During 2009 to 2014 he collaborated in ClariPhy Argentina SA in the design and implementation of digital blocks for generations of chips for fiber optic systems from 10 Gbps to 600 Gbps.

Between 2013 and 2015, he collaborated in Fundación Fulgor in the development of a prototype for a Satellite Proximity-1 Modem for the SARE’s mission to the Comisión Nacional de Actividades Espaciales (CONAE).

He is currently member of the research staff at ClariPhy Argentina SA and Fundacion Fulgor. His research interests include high-speed architectures analysis for digital communication receivers, digital signal processing, and implementation of communication systems in ASIC and FPGA.


Ing. Nicolás Álvarez (UNSAM-FIUBA) is an electronic engineer from the University of Buenos Aires. He is a Regular Lecturer at the University of Buenos Aires, in the Digital Systems course, and Head of Practical Work with exclusive dedication at the National University of San Martín, at the Digital Electronics I and Digital Electronics II courses. He has participated in different projects agreements between the UBA and different institutions, such as the Faculty of Medicine of the UBA or CONAE.

He has taken postgraduate courses in Computer Security at the University of Buenos Aires and has participated in various courses and seminars in topics related to the design of Finite State Machines, functional verification of digital systems, voice over IP, among others. He has directed or participated as a jury in more than 8 thesis in electronic engineering.


Ing. Federico Zacchigna (FIUBA) has a degree in Electronic Engineer from the Engineer Faculty of the the University of Buenos Aires (2012), and aspiring to the title of PhD. in Engineering by the University of Buenos Aires. He is a lecturer in the Semiconductor Devices course in the electronic engineering career at FIUBA and is a lecturer in the FIUBA embedded systems specialization course.

He has participated in several projects as integrande of the Laboratory of Embedded Systems and has dictated several courses in Digital Systems for companies and in different congresses and symposiums.

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