Advanced Digital Design

Goal


To give the student the knowledge about the problems and tools related to the design of specific application integrated circuits (ASIC), including problems related to time, performance and power optimization, and verification tests.

Let the student understand the theory and tools involved in designing large-scale digital integration systems (VLSIs) for architectures with millions of transistors.

That the student learn to use the Hardware Language for the design of digital systems.

That the student understands the different Design metrics: number of devices and area of ​​implementation, switching speed, energy dissipation and power.

Minimum Content

Introduction to the digital world and ASIC design flow
Design of digital systems using VerilogHDL
Finite State Machines
Time Related Design
Hierarchy and Partitioning
Low Power Design
Test, simulation and testbench design

Schedule

Download the schedule in this link!

Teaching Team

Ing. Victor Grimblatt (UCh–UANDES) has an engineering diploma in microelectronics from Institut Nationale Polytechnique de Grenoble (INPG – France) and an electronic engineering diploma from Universidad Tecnica Federico Santa Maria (Chile). He is currently R&D Group Director and General Manager of Synopsys Chile, leader in Electronic Design Automation (EDA). He opened the Synopsys Chile R&D Center in 2006. He has expertise and knowledge in business and technology and understands very well the trends of the electronic industry; therefore he is often consulted for new technological business development.

Before joining Synopsys he worked for different Chilean and multinational companies, such as Motorola Semiconductors, Honeywell Bull, VLSI technology Inc., and Compass Design Automation Inc. He started to work in EDA in 1988 in VLSI Technology Inc. where he developed synthesis tools being one of the pioneers of this new technology. He also worked in embedded systems development in Motorola semiconductors.

In 1990 he was invited by professor McCluskey to present his work in Logic Synthesis at the CRC – Stanford University. He has published several papers in EDA and embedded systems development, and since 2007 he has been invited to several Latin American Conferences (Argentina, Brazil, Chile, Mexico, Peru and Uruguay) to talk about Circuit Design, EDA, and Embedded Systems. From 2006 to 2008 he was member of the “Chilean Offshoring Committee” organized by the Minister of Economy of Chile. In 2010 he was awarded as “Innovator of the Year in Services Export”. In 2012 he was nominated to best engineer of Chile. He is also member of several Technical Program Committees on Circuit Design and Embedded Systems. Since 2012 he is chair of the IEEE Chilean chapter of the CASS. He is also the President of the Chilean Electronic and Electrical Industry Association (AIE)

Victor Grimblatt was professor of Electronics and IC Design in Universidad de Chile and Universidad de los Andes.


Ing. Esteban Viveros Esteban Viveros is an Electronic Engineer from the Universidad de Concepción (Concepcion, Chile). He started to work at Synopsys Chile in December 2013 as Quality Engineer in the Product Validation team, part of the Design Group. His work is mainly related to quality assurance of the Synopsys synthesis tools (Design Compiler, Power Compiler, DFT Compiler, etc.). He actively collaborates on developing training material for Synopsys Chile training activities.







Ing. Gonzalo Fernandez is an Electronic Engineer from the Universidad de Concepción (Concepcion, Chile). He is part of the multicultural Power Compiler CAE team (EEUU, India, Chile) which is in charge of ensuring quality of Design Compiler (Synopsys Logic Synthesis Tool), with respect to the Low Power and Multi-Voltage flows. These flows are based on the IEEE 1801 standard (UPF). He is also part of the team from Synopsys Chile that develops and deploy trainings.

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