Archive for the Category "CAMTA 2013".

camta poster sessions

Jueves, Agosto 8th, 2013

Each year, has several authors presenting the latest results of their researchs. This year, 18 IEEE posters plus 3 student posters are presented between Thursday 15 and Friday 16.
The Paper Titles, Authors and schedules are displayed below.

camta program

Miércoles, Agosto 7th, 2013

CAMTA Program

In this year’s edition, CAMTA will be honored with several guests and industry representatives. Each one will have a one hour slot to provide the assistants with the latest trends in the Microelectronics Industry and the state-of-the-art in several Research Fields.

grants results EAMTA 2013

Viernes, Julio 12th, 2013

Grants Results

Grants Results:

Distinguished Guests CAMTA 2013

Jueves, Mayo 30th, 2013

Distinguished Guests

As usual, the CAMTA 2013 has several distinguished Authorities, Researchers and Industry-representative figures. Also, these days poster sessions are held, showing the latest trends and state-of-the art results in several research fields. Below are the CAMTA Program and the CAMTA poster Session schedules, due in Thursday 15 and Friday 16.

  • CAMTA Program
  • CAMTA Poster and Papers Session

    Dintiguished Authorities At CAMTA 2013

  • Dr. Roberto Carlos Salvarezza
  • Fue técnico, becario, investigador y director. El nuevo presidente del Conicet, Roberto Salvarezza, es un bioquímico recibido en la UBA. Actualmente el es presidente del CONICET.

    Dintiguished Guests At CAMTA 2013

  • Allegro Microsystems
  • Unitec Blue
  • Synopsys
  • Clariphy
  • Cadieel
  • mems rad track 2013

    Miércoles, Mayo 15th, 2013

    Maximum limit of participants: 18


    The main goal of this track is to introduce the assistants to the fascinating, new world of Micro-Electronic Machines, and to familiarize with concepts, jargon and technologies.
    Also, assistants will have the opportunity to assist to a Clean Room and engage in the design of their own MEMS (to be confirmed). Radiation hardened design (Rad-hard) and radiation effects will also be discussed, and different investigation lines will be presented.


    Introduction to MEMS
    Latest developments in commercial MEMS
    Radiation Effects on Semiconductors and MOS.
    RAD-HARD design.


    Hernan Pastoriza.
    Felix Palumbo.
    Lliana Fraigi.
    Laura Malatto.
    Alex Lozano.


    To be confirmed.

    advanced digital track 2013

    Miércoles, Mayo 15th, 2013

    Maximum limit of participants: 30


    To prepare the student to be an entry-level industrial standard cell ASIC designer.
    To give the student an understanding of issues and tools related to ASIC design and implementation including timing, performance and power optimization, verification and manufacturing test.
    To give students the understanding, theory, and tools necessary to design large-scale digital system VLSI design for architectures that have millions or billions of transistors
    To use a Hardware Design Language (Verilog) for digital design
    To understand different design metrics: component/gate count and implementation area, switching speed, energy dissipation and power


    Introduction to digital world and ASIC design flow
    Design of digital hardware using Verilog HDL
    Finite State Machines
    Timing Design
    Hierarchy and Partitioning
    Low Power Design
    Test Benches and Verification


    The track considers labs where the students will develop specific modules using Verilog and state-of-art design tools


    Victor Grimblatt
    Victor has a Microelectronic Engineering degree from the Institut National Polytechnique de Grenoble (France) and an Electronics Engineer degree from Universidad Santa Maria (Valparaiso, Chile). He has more than 20 years experience in the electronics and information technology industry working in several international companies such as VLSI technology Inc, Compass design Automation Inc, Honeywell Bull, Motorola and Synopsys Inc. in France, USA, and Chile. He is now managing an R&D Center Synopsys opens in Chile. He is also professor at Universidad de Chile and Universidad de los Andes where he lecture courses related to Digital Systems, Computer Architecture, Integrated Circuit Design, and Embedded Systems.

    To be defined
    To be defined

    Class materials

    All the material will be provided to students during the EAMTA.


    M.D. Ciletti, “Advanced Digital Design with the Verilog HDL,” (Prentice Hall), 2003. ISBN 0-13-089161-4.
    D.R. Smith and P.D. Franzon, “Verilog Styles for Synthesis,” (Pearson Education [Prentice Hall]), 2000.ISBN. 0-201-61860-5.
    Thomas and Moorby, “The Verilog Hardware Description Language”, 3rd edition, Kluwer Academic. ISBN 0-7923-9723-1.
    S. Sutherland, S. Davidman, P. Flake, “System Verilog for Design” (Kluwer), 2004, ISBN 1-4020-7350-8.
    H. Bhatnagar, “Advanced ASIC Chip Synthesis Using Synopsys Design Compiler, Physical Compiler, and PrimeTime”, ISBN 0-7923-7644-7.
    Samir Palnitkar, “Verilog HDL” (Prentice Hall), 2008. ISBN 0-13-044911-3
    John Willimas, “Digital VLSI Desing with Verilog” (Springer), 2008, ISBN 978-1-4020-8445-4

    advanced analog track ii 2013

    Miércoles, Mayo 15th, 2013

    Maximum limit of participants: 30


    This year, an advanced Analog Design Track will be offered to complete the analog training of students based on a short course of “High-speed transceivers” and a tutorial on High Speed VCO design and PLL Design. Also, this course will be complemented with “Ultra Low voltage Design”, and “Software Defined RF Electronics” The course will be interspersed with Analog Design Tutorial using Synopsys

      High speed PLL and VCO design

      To be completed soon.

    1. Lecturers

      Mahyar kargar
      Burak Catli
      Geza kolumban
      Carlos Galup-Montoro

    Synopsys Custom Design Tutorial

      Day 1:

        Custom Designer Overview
        Invoke and exit Custom Designer
        Open a design
        Navigate the GUI windows to view objects of interest
        Use Preference Manager GUI
        Viewport navigation using Bookmarks manager
        Use Display Resources Editor GUI

        Library Manager
        Create Libraries, Cells and CellViews
        Create and manage cell categories
        Editing functions to manage library, cell, and cellviews
        Handle technology data
        Create parameters

        Schematic Editor:
        Lab 1 – Basic Schematic Entry – CMOS Differential Amplifier
        Create and place Instances
        Edit using editing functions
        Edit the instance parameters
        Create Pins
        Create Wire Objects
        Create Wire Names
        Check and Save the Design

        Lab 2 – Basic Symbol Generation
        Create the symbol
        Edit the symbol
        Add Selection Shape
        Check the symbol
        Save the symbol

        Lab 3 – Test Bench Creation
        Understand the need of a test bench.
        Create a test bench.

        Lab 4 – Netlisting and Simulation Interface using HSPICE
        Launch the simulation interface
        Setup the inputs
        Netlist the design
        Simulate the design
        View waveforms using WaveView

        Lab 5 – Hierarchical Data Creation and Design Navigation
        Create a design hierarchy using symbols.
        Traverse the hierarchy.
        Use Bookmarks and Edit in Place features to quickly access and edit design information.

      Day 2:

        Lab 6 – Basic Configuration View Creation
        Create and Edit the Configuration View
        Define and use the various selection rules and bindings

        Lab 7 – Parameterized Connections
        Understand the concept of parameterized connections
        Create connection definitions
        Override and redefine the connection definitions
        Use the concept when designing

        Layout Editor
        Lab 1 – Basic Cell Design Creation – Inverter
        Set and use grids for drawing shapes.
        Create layout using design rule-guided data creation functions.
        Use different usage models of data creation functions.
        Edit using design rule-guided editing functions.
        Use Object Layer Panel to select LPP for shapes creation.
        Create Pins.
        Create Labels.
        Create Boundaries.

        Lab 2 – Physical Verification Interface
        Customize the required options for Hercules DRC/LVS.
        Execute Hercules DRC/LVS from within Custom Designer.
        View and debug errors using the error viewer VUE.
        Fix DRC/LVS errors using editing functions.

      Day 3

        Lab 3 – Design Creation using Pcells – CMOS Differential Amplifier
        Create Pcell instances.
        Edit Pcell parameters.
        Use Abutment functions to overlap/abut pin shapes.
        Use Align function to align any object to another object.
        Create paths or pathsegment interconnects.
        Edit paths or pathsegment interconnects using editing functions.
        Create MultiPartPaths.

        Lab 4 – Hierarchical Design Creation and Navigation – VCO
        Build a hierarchical design
        Use Hierarchy Navigator assistant to
        View the hierarchy tree of a design
        Open the design at any level of hierarchy
        Use Hierarchy toolbar to
        Ascend/ Descend at different levels of hierarchical design for editing or in read mode
        Select the view type of the child cell for editing

        Lab 5 – Parasitic Extraction Interface – VCO
        Customize the required options for Star-RC
        Execute Star-RC
        Explore the parasitic extracted view
        View and analyze the extracted parasitics

        Additional topics:
        Simulation and Analysis Environment (SAE) overview
        Schematic Driven Layout (SDL) overview

    advanced analog i track 2013

    Miércoles, Mayo 15th, 2013

    Maximum limit of participants: 30


  • Dr. Alfredo Arnaud (Universidad Católica de Montevideo-Uruguay)
    Curso de diseño de circuitos integrados con tecnologia HV orientado a aplicaciones médicas implantables
    Para mas información Click aquí
  • Dr. Carlos Dualibe (Université de Mons, Bélgica).
    Filtros gm-C
    Conversores AD/DA
  • Dr. Fernando Silveira (Universidad de la República de Uruguay)
    Circuitos para bajo consumo.
  • Dra. Rafaella Fiorelli (Universidad de Sevilla, España)
    RF Blocks.
  • Material de clases

    Material del Curso: gmc Dualibe
    Material del Curso: RF Blocks
    Ejercicios del Curso: RF Blocks

    basic design track 2013

    Miércoles, Mayo 15th, 2013


    Maximum limit of participants: 120


    Introducción al diseño digital.
    Física de Dispositivos MOS.
    Introducción al diseño analógico.


    -Dr. Pedro Julián.
    -Mg. Luis Toledo.
    -Mg. Pablo Petrashin.


    El track incluye el trabajo en laboratorio diseñando un circuito integrado, usando software CAD. Habrá un número limitado de vacantes según la disponibilidad de computadoras. Se sugiere inscribirse en este track a aquellos participantes que no tengan experiencia en el diseño de circuitos integrados o no hayan asistido a ediciones previas de la EAMTA.

    Material de clases:

    Material de clases de Pedro Julián, Introduccion a VLSI.

    Filminas y Problemas de VLSI: VLSI_1VLSI_2VLSI_3

    Clases, apuntes y Filminas de Petrashin y Toledo.

    Material de Laboratorio:

    Tutoriales para Laboratorio de Track Básico

    Libro de dispositivos semiconductores

    Pedro Julián

    eamta 2013 awards

    Sábado, Abril 27th, 2013

    EAMTA 2013 Contest and Awards


    Two grants will be given to the best two IC design proposal during EAMTA 2013, as part of the effort to promote IC design in Argentina.
    Participants can team up to present a proposal that should be sent by email or in person before August 15th. The authors of the proposal must be EAMTA participants or have been participants of one of the past editions.
    The award will consist of chip fabrication, 500USD for materials, development and packaging of the parts.
    The proposal should describe the project, estimated size of the design and propose a schedule for the development
    (the development must begin AFTER EAMTA). It is strongly recommended that the design has some commercial target, and the authors are encouraged to discuss with companies, professors, investors and engineers present during EAMTA. It is also recommended for the teams to get a company sponsor and a professional willing to serve as tutor of the project. These items will be considered when rating the projects.
    There will be two awards:

    The MOSIS Award

    The MOSIS award will include fabrication in the ON Semi CMOS 0.5um technology.

    Premio MOSIS:
    El premio MOSIS incluirá la fabricación de un chip en
    tecnología CMOS 0.5um.

    The TowerJazz Award

    TowerJazz will offer One free Shuttle run in TS18PM/TS35PM technology, with the following features:
    a. Up to $5000 USD worth process (up to 30 process layers).
    b. Maximum area is 8mm2
    c. Deliverables are 20 die samples
    d. High performance standard cell library available

    Regarding Handling of IC packaging and shipping:
    a) Shipping of dies is included but can be arranged and shipped to Argentina.
    b) The cost of packaging is not included. This cost can be covered by theLMNE. Participants should justify solidly the choice of technology.

    EAMTA 2012 Awards

    Click here to see EAMTA’s 2012 Contest and Award WINNERS