Paper Sessions

CAMTA 2017 paper sessions

Paper sessions will take place on Thursday, July 27 at Teatro Tornavías.

X-ray Micrographic Imaging System Based on COTS CMOS Sensors
Martín Pérez, José Lipovetzky, Fabricio Alcalde Bessia, Mariano Gómez Berisso

This paper presents the use of Commercial Off The Shelf CMOS image sensors for the acquisition of x-ray images with high spatial resolution. The x-ray images, with application in biology, electronic components inspection or paleontology research, are obtained with 8 keV photons from a Cu tube. The quantum efficiency of the detector is estimated using attenuation lengths of photons in the sensor, and compared to traditional scintillator conversion layers.
Time: 10:00
Room: Teatro Tornavías

Setup and Calibration of a particle detector based on Charge Coupled Devices
Elodie Tiouchichine, Miguel Sofo Haro, Xavier Bertou, Horacio Arnaldi, Mariano Gomez Berisso, Jeronimo Blostein, Javier Tiffenberg, Martin Perez, Sergio Suarez, Guillermo Fernandez Moroni

Thick Charge Couple Devices have proven to be interesting particle detectors. The DAMIC and CONNIE collaborations are using this technology to search for the elastic scattering of a dark matter particle or a neutrino with a silicon nucleus, producing a nuclear recoil. The experiments reach unprecedented sensitivity at low energies (below 100\,eV) by taking advantage of the low readout noise achieved by these devices. The present document describes an experimental setup at the Centro Atómico Bariloche, its noise treatment and its calibration.
Time: 10:20
Room: Teatro Tornavías

Programmable PLL-Based Frequency Synthesizer: Modeling and Design Considerations
Rahael Ronald Noal Souza, Agord De Matos Pinto Junior

This work presents the set of structure and operating features for a third-order Charge Pump Phase-Locked Loop CP-PLL-based Frequency Synthesizer for clock generation. For implementation purpose, a new architectural solution for N integer frequency division is proposed considering the particular design requirements in the PLL feedback for operation with different reference input frequencies FREF. The proposed CP-PLL was designed at Cadence Analog Design Environment ADE by applying standard CMOS-based technology (UMC L180). From the PLL settings at simulation environment, circuit level results indicates a settling time TS < 3 µs at power supply VDD = 1.8 V, considering the divide ratio N variation (4-16) for a range of input frequencies (20 to 50 MHz).
Time: 10:40
Room: Teatro Tornavías

Coffee Break (20 minutes)

Integrated Potentiostat for Detection of Chagas Disease
Fabian Torres, Leonardo Agis, Joel Gak, Matías Míguez

he design of a low power integrated potentiostat that measures electric current, intended for a Chagas disease detection application is presented. The circuit was designed using 0.6μm XC06 technology from XFAB [1]. This circuit can generate and measure currents from 1 to 10μA with a relative error under 1%. The remaining part of the circuit consumes only 1.5μA. The total silicon area is 0.24mm2 (without pads)
Time: 11:20
Room: Teatro Tornavías

Charge trapping effects on Metal-Gate/High-k/III-V MOS devices assessed through C-V
Sebastián Matías Pazos, Fernando Leonel Aguirre, Felix Palumbo

n this work, the differences in the trapping/detrapping characteristics of Metal-Gate/High-k/III-V MOS stacks is experimentally studied by means of the C-V Hysteresis and dynamic stress. Samples under study include the combination of n-InP and n-InGaAs substrates with HfO2 or Al2O3 dielectrics as gate oxides. This allows to assess the impact of both the substrate and the dielectric on the quality of the complete structure. Results show that Al2O3-based stacks exhibit lower overall trapped charge during hysteresis cycles than their HfO2 counterparts. Additionally, InP-based samples introduce a larger amount of defects above the fermi-level when compared to InGaAs samples for positive stress, but with negligible trapping effects when stressing towards inversion, which is a positive indicator in terms of reliability.
Time: 11:40
Room: Teatro Tornavías

Automatic ASET sensitivity evaluation of a custom-designed 180nm CMOS technology Operational Amplifier
Andrés Fontana. Sebastián Pazos, Fernando Aguirre, Félix Palumbo

This work presents a SPICE-based automatic ASET sensitivity evaluation of a 180nm CMOS full-custom Operational Amplifier. The set-up uses the well known double exponential current law to inject SET into every sensitive node in the circuit hierarchy. The pulse parameters are obtained according to a previously generated population of particles with randomly assigned energies and species, the node bias condition at the instant of the strike and an empirical model obtained through TCAD simulations. The circuit is evaluated transistor-wise for each ion of the generated database and the output waveforms are processed in time and frequency domain to obtain figures of merit of the hardness of the proposed design on a given radioactive environment. Results allow to identify the most sensitive devices and the expected error rate for the projected application, allowing to conduct hardening techniques during early design stages.
Time: 12:00
Room: Teatro Tornavías

Design and Characterization of a CMOS Two-Stage Miller Amplifier for Ionizing Radiation Dosimetry
Guido Salaya, Mariano Garcia Inza, Sebastián Carbonetto, Adrian Faigon

The offset of an operational amplifier -its inability to yield zero output at zero input- is mainly due to an imperfect mismatch between its inputs. If through some physical perturbation on the circuit we could increase this mismatch, the amplified offset measured at the circuit output would be a measure of that perturbation. This is the idea to be tested in this work: the perturbation is exposition to ionizing radiation, the increasing mismatch is got by proper polarization of each one of the MOS transistors at the operational amplifier input while being irradiated, the quantity to be measured: the dose, deposited energy on the matter from the ionizing field.

The work presents a theoretical analysis in order to establish the expected effects of radiation on the different blocks of operational amplifiers, describes the design and fabrication of an integrated circuit to be tested, the design and assembly of a dedicated hardware and software to collect measurement data, and first results.
The fabricated dosimeter in CMOS 0.6 um commercial CMOS technology exhibits a sensitivity of about 60 mV/Gy and resolution of 4 cGy.
Time: 12:20
Room: Teatro Tornavías

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